Improved tuning methods for converter modulators

This paper will review the results of this investigation based on models developed from the SNS converter-modulator operational data.

Authors Close. Assign yourself or invite other person as author. It allow to create list of users contirbution. Assignment does not change access privileges to resource content. Wrong email address. You're going to remove this assignment. Are you sure? Yes No. Los Alamos Nat. Keywords switching convertors circuit tuning modulators power semiconductor switches PWM power convertors resonant power convertors frequency 1 kHz tuning methods resonant power configuration load impedance insulated gate bipolar transistors IGBT resonant switching topology SNS spallation neutron source pulse width modulation PWM converter-modulator operation power 10 MW to 15 MW switching convertors circuit tuning modulators power semiconductor switches PWM power convertors resonant power convertors frequency 1 kHz tuning methods resonant power configuration load impedance insulated gate bipolar transistors IGBT resonant switching topology SNS spallation neutron source pulse width modulation PWM converter-modulator operation power 10 MW to 15 MW.

Additional information Data set: ieee. Publisher IEEE. Article :. Date of Publication: 26 November DOI: Need Help? A plurality of MOS transistors is used to construct the varactor A cross-sectional side view of one such transistor 20 is shown in FIG. As shown in FIG. The gate oxide 28 and the polysilicon gate 30 are defined by suitable dielectric spacers 32 and Thus, the varactor 10 has a plurality of gates In accordance with the varactor 10 as shown in FIG.

A first metal layer 40 is electrically coupled to each of the gates The varactor 10 , whose equivalent circuit is shown in FIG. As can be seen from FIGS. The capacitance of the varactor 10 varies according to the voltage applied across the first and second metal layers 40 and As this voltage increases, the varactor 10 moves from the depletion mode to the inversion mode. During this operation, the potential on the body of the transistor i.

The varactor 10 covered by the graph of FIG. Certain modifications of the present invention have been discussed above. Other modifications will occur to those practicing in the art of the present invention. For example, as described above, the varactor 10 is formed on an SOI structure. Instead, the varactor 10 may be formed on bulk silicon or SOS silicon-on-sapphire.

Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved.

The method of claim 1 wherein each of the silicon gates comprises a polysilicon gate.